Time varying signals in electronic devices are utilized to transfer information (e.g., data) over one or more conductors often referred to as signal lines. These signal lines are often bundled together to form a communications bus, such as an address or data bus, for example. Termination is often used on these busses in order to reduce certain transmission line effects due to various electrical properties of the bus. For example, a mismatch in characteristic impedance of two signal lines coupled together can result in reflections. Capacitive and inductive effects can also cause undesirable issues with signal integrity. Thus, it is typically desirable to reduce these effects in order to reduce the likelihood of data corruption as the data is transmitted on a bus.
Memory devices are an example of devices which often utilize address and data busses. Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones, and removable memory modules.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged and accessed. Typically, the array of memory cells for NAND flash memory devices is arranged such that memory cells of a string are connected together in series, source to drain.
To meet the demands for higher data read and write transfer rates, designers continue to strive for increasing the access speed of memory devices and systems. Memory systems often are comprised of multiple memory device packages (e.g., die) which are coupled together on a common circuit board and communicate on a common data bus, for example. However, one issue with increased data transfer rates is maintaining signal integrity during these bursts of data on the various bus signal lines of the memory system. As these transfer rates increase, the impedance characteristics of a data bus become more pronounced. Capacitive and inductive characteristics of the circuit board may begin to distort the signal waveforms on the data bus at these higher data rates. Waveforms may begin to spread out and/or reflections may occur at locations of unmatched impedance on the data bus signals, for example.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative termination methods and apparatus in various memory device architectures.